PHYS598500 ยท 2026 Fall ยท 16 weeks

Superconducting Quantum Computer Architecture

Advanced Superconducting Quantum Computer Architecture

Course Positioning

The course proceeds from the computation model to the qubit Hamiltonian, then sequentially addresses qubit design, control, coupling, readout, calibration, benchmarking, stabilizer QEC, surface-code cycle, cryogenic systems, electronics, packaging, fabrication processes, and a full-system capstone.

Full-Semester Course Map ยท v5

Building Quantum Computing into a Machine

T1How Computation Becomes Physical Operations
W1From Algorithms to Hardware Operations
(Draft)
T2Fabricating Qubits from Circuits
W2Turning Circuits into Transmons W3Charge Noise and Fluxonium
T3Controlling, Coupling, and Reading Out Qubits
W4Controlling a Single Qubit with Microwaves
(Draft) W5Enabling Interaction Between Two Qubits
(Draft) W6Translating Quantum States into Signals
(Draft)
T4Calibration, Verification, and Quantum Error Correction
W7Identifying and Calibrating Chips
(Draft) W8Measuring Errors and Performance
(Draft) W9Detecting Errors Using Syndromes
(Draft) W10 QEC Quantum Error Correction
(Draft)
T5Cryogenics, Signal, and System Integration
W11Cooling the Chip and Managing Heat Flow
(Draft) W12Routing Control and Readout Signals In and Out
(Draft) W13Packaging, Wiring, and Scalability
(Draft)
T6Stabilizing Designs into Chips
W14Fabricating Layouts into Chips
(Draft) W15Controlling Material Losses and Process Variations
(Draft)
T7Integrating a Complete Quantum Computer
W16Making Comprehensive System Architecture Choices
(Draft)

Theme Configuration

Theme Positioning Weeks
T1 Principles 1 Week
T2 Qubit Physics 2 Weeks
T3 Control & Readout 3 Weeks
T4 Calibration & QEC 4 Weeks
T5 Full-System Architecture 3 Weeks
T6 Fabrication 2 Weeks
T7 Frontier & Capstone 1 Week

W1โ€“W16 ยท Question Map

Core Teaching Questions per Week

Review the full semester sequence; adopt a modular structure with one major theme per week, divided into 5โ€“6 subtopics, each roughly corresponding to a 20-minute lecture segment.

T1

From Computational Models to Physical Operations

Principles

W1 From Quantum Computational Models to Hardware Operations(Draft) 6 Questions

  1. What exactly does a step in a quantum algorithm require the hardware to do?

  2. Why must closed quantum evolution be unitary and therefore reversible?

  3. How does a logical gate become a decomposable unitary operation?

  4. How is a unitary operation generated by a time-dependent Hamiltonian?

  5. Where do measurement, reset, and classical feedback interface with the unitary chain?

  6. Along which abstraction layers will subsequent courses track errors and resources?

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T2

Fabricating Qubits from Circuits

Qubit Design

W2 Quantization of Superconducting Circuits and Transmon Design 5 Questions

  1. What Are Artificial Atoms?

  2. How Do We Quantize a Circuit?

  3. How Do We Select the Computational Subspace?
    \(\to\) Anharmonicity and the Josephson Junction

  4. How Do We Make a Qubit Tunable?
    \(\to\) SQUID and Tunable Qubits

  5. Why Did the Transmon Become the Mainstream Superconducting Qubit?
    \(\to\) Charge-Noise Suppression and the Anharmonicity Trade-off

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W3 Fluxonium: From Circuit Modification to Design Trade-offs 6 Questions

  1. Why add a superinductor beyond the Transmon circuit?

  2. Selection rule

  3. How does inductive energy modify the potential and energy spectrum?

  4. How does external flux alter the operating point and wavefunction?

  5. Which noise sources are suppressed by Fluxonium, and what costs are introduced?

  6. Under what conditions should Fluxonium be chosen over Transmon?

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T3

Controlling, Connecting, and Reading Out Qubits

Control & Readout

W4 Single-Qubit Control: From Microwave Pulses to the Rotating Frame(Draft) 6 Questions

  1. How do room-temperature I/Q waveforms translate into target qubit rotations?

  2. What aspects of the drive are controlled by frequency, phase, amplitude, and duration?

  3. Why do the rotating frame and RWA simplify control problems?

  4. Why do pulses cause leakage and waveform distortion?

  5. How to calibrate a rough pulse into a verifiable Xฯ€/2 gate?

  6. Which observables can distinguish amplitude, detuning, phase, and distortion errors?

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W5 Coupling Hamiltonians, Two-Qubit Gates, and Tunable Couplers(Draft) 6 Questions

  1. How to enable interaction between two qubits only when needed?

  2. What terms do different coupling circuits introduce into the Hamiltonian?

  3. What are the differences between exchange, ZZ, and avoided crossing interactions?

  4. Under what conditions should iSWAP, CZ, or cross-resonance gates be selected?

  5. How do spectator errors, crosstalk, and frequency collisions scale with chip size?

  6. How to translate a connectivity graph into interaction requirements and an error budget?

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W6 Circuit QED, Dispersive Readout, and the Measurement Chain(Draft) 6 Questions

  1. How to convert invisible quantum states into classifiable voltages?

  2. How is qubitโ€“resonator coupling described by the Jaynesโ€“Cummings model?

  3. How do dispersive shift, readout contrast, and Purcell loss constrain each other?

  4. How does a quantum state propagate through the resonator, amplifier, and IQ classifier?

  5. How to establish a signal-to-noise budget from the readout tone to the IQ cloud?

  6. How should readout speed, fidelity, and backaction be jointly validated?

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T4

Calibration, Verification, and Protection of Quantum Information

Calibration & QEC

W7 Quantum Processor Calibration: Hamiltonian Identification and Drift(Draft) 6 Questions

  1. Which parameters must be determined first after powering up the quantum chip?

  2. In what dependency order should spectroscopy, Rabi, Ramsey, T1/T2, and readout be executed?

  3. How to transform measure โ†’ fit โ†’ update โ†’ validate into a calibration graph?

  4. For how long can a set of calibration parameters be trusted under drift?

  5. How does frequency drift corrupt downstream gates and readout?

  6. What must a minimal operational calibration dependency graph contain?

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W8 Benchmarking, Multi-Qubit Errors, and Scalable Calibration(Draft) 6 Questions

  1. What failure modes might be hidden by a high average fidelity?

  2. What do RB and interleaved RB actually measure?

  3. What noise assumptions does the RB decay model rely on?

  4. How to distinguish leakage, crosstalk, and correlated errors?

  5. Why might a single gate perform well while an entire circuit layer performs poorly?

  6. How to map each benchmark metric to a falsifiable failure hypothesis?

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W9 Foundations of Quantum Error Correction: From Physical Errors to Stabilizer Syndromes(Draft) 6 Questions

  1. Are physical errors and computational failures the same thing?

  2. Since quantum information cannot be cloned, where does redundancy come from?

  3. How to detect errors without directly measuring the answer?

  4. What information do stabilizers actually compress?

  5. What does code distance guarantee, and what does it not guarantee?

  6. Why is the surface code needed next?

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W10 Surface-Code Hardware Cycle: Scheduling, Decoding, and Logical-Qubit Resources(Draft) 6 Questions

  1. Why is the surface code suitable for superconducting quantum chips?

  2. How should a round of syndrome extraction be scheduled?

  3. Syndrome measurements themselves can fail; how do we handle this?

  4. How fast must the decoder be?

  5. Does reducing physical error rates guarantee a reduction in logical error rates?

  6. What are the actual hardware and classical resource requirements for a single logical qubit?

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T5

Integrating Cryogenics, Signals, and System Operation

Full-System Architecture

W11 Dilution Refrigerators, Thermalization, and Cryogenic Line Budgets(Draft) 6 Questions

  1. How to deliver signals without introducing heat and noise into the 10 mK stage?

  2. What cooling power is available at each temperature stage of a dilution refrigerator?

  3. How to establish budgets for conduction, dissipation, radiation, and device heat load?

  4. How should drive, flux, and readout lines be attenuated, filtered, and thermalized?

  5. How to construct stage-by-stage thermal and noise budgets for the three types of lines?

  6. How to use budgets to determine component placement rather than memorizing cryogenic part names?

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W12 Microwave Control, Readout Electronics, and Signal Integrity(Draft) 6 Questions

  1. How do electronic instrument specifications translate into quantum errors?

  2. How do DACs, AWGs, LOs, IQ mixers, and clocks form the control chain?

  3. How to establish gain, noise, and dynamic-range budgets for an amplifier cascade?

  4. What intermodulation, ADC, and classification issues arise in multiplexed readout?

  5. How to derive electronics requirements from readout targets?

  6. How to validate the signal-integrity chain from room temperature to the qubit?

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W13 Packaging, EM Modes, Wiring Scalability, and Full-System Integration(Draft) 6 Questions

  1. As qubit counts increase, why does packaging become part of the Hamiltonian?

  2. How do package cavities, slotlines, ground returns, bond wires, and seam losses affect qubits?

  3. How to establish acceptance criteria based on EM modes and participation ratios?

  4. How do I/O density, heat load, 3D wiring, and cryogenic control jointly limit scalability?

  5. How to conduct a package/wiring architecture review for a 100-qubit system?

  6. Which three budgets are most likely to be exceeded first as the system scales?

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T6

Stabilizing Designs into Chips

Fabrication

W14 Superconducting Quantum Chip Fabrication and Josephson Junction Process Module(Draft) 6 Questions

  1. How are $E_J$ and $E_C$ on the layout physically realized by the fabrication process?

  2. How do substrate, base metal, lithography, etch, lift-off, and cleaning form the process flow?

  3. How to establish a Josephson junction process module from $R_n$, $I_c$, and $E_J$?

  4. How are PCM, overlay, residue, and surface treatment validated at cryogenic temperatures?

  5. Which CTQs, PCMs, and defects should be monitored for each process step?

  6. How to establish a mapping from design parameters to process control?

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W15 Materials Loss, Process Variation, Yield, and the Designโ€“Fabโ€“Measure Loop(Draft) 6 Questions

  1. How to translate "this qubit is bad" into reproducible process knowledge?

  2. How do TLS, surface/interface loss, quasiparticles, and participation ratio affect $T_1$?

  3. How to derive frequency collision and chip yield from process variation distributions?

  4. How do split lots, PCM, and cryogenic testing form the designโ€“fabโ€“measure loop?

  5. How to design a split-lot experiment for frequency spread or $T_1$ tail?

  6. How to shift from pursuing the best device to managing a manufacturable distribution?

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T7

Integration into a Complete Quantum Computer Architecture

Capstone

W16 Frontier Architectures and Hardware-Aware Quantum System Capstone(Draft) 6 Questions

  1. How should the overall architecture be selected for practical quantum computing?

  2. How to derive logical-qubit, error, and latency requirements from workloads?

  3. How to allocate code, qubits, coupling, and control downward from logical requirements?

  4. How to compare modular designs, 2D/3D I/O, cryo-control, and different qubit branches?

  5. How to conduct an overall architecture review of the QPU, control, fabrication, and QEC?

  6. How to distinguish between demonstrated, projected, assumed, and kill criteria?

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Peir-Ru Wang PHYS598500
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