Hardware Guide

When we discuss “ultra-large-scale quantum computing,” it is natural to imagine a gigantic quantum computer with hundreds of thousands, or even millions, of qubits. However, a truly usable quantum computing system will not simply be an isolated cryogenic instrument. It will more closely resemble a quantum-centric supercomputer that integrates high-performance computing (HPC), classical control systems, cryogenic quantum processors (QPUs), real-time decoders, and cloud-based scheduling software.

In this architecture, quantum computers do not replace conventional supercomputers. Instead, they become specialized accelerators within high-performance classical computing systems. CPUs and GPUs are responsible for data preprocessing, parameter optimization, error mitigation, result analysis, and workflow management; QPUs are responsible for handling subproblems with intrinsically quantum structure, such as quantum chemistry, materials simulation, combinatorial optimization, or specific linear-algebra tasks.

From Standalone Quantum Computers to Quantum-Centric Supercomputers

The scaling path of classical computers has evolved from single processors to multicore processors, clusters, data centers, and supercomputers. Similarly, quantum computers are unlikely to remain forever in the form of “a single chip + a single cryostat.” As the number of qubits increases, the system simultaneously faces bottlenecks in cryogenic space, control-line count, readout bandwidth, calibration complexity, thermal load, and the speed of error-correction decoding.

Therefore, future large-scale quantum computing will likely adopt a hybrid architecture: classical supercomputers will handle massive data flows and control decisions, while subproblems suitable for quantum acceleration will be sent to QPUs. This is not a competition of “quantum vs. classical,” but a collaborative model of “quantum + classical” computing.

System Layer	Primary Role	Function in Hybrid Quantum Computing
CPU	General-purpose classical computing core	Responsible for program scheduling, data preprocessing, iterative control, algorithm workflow management, and communication with cloud or HPC systems.
GPU	Massively parallel computing core	Responsible for tensor operations, linear algebra, machine learning, gradient estimation in variational algorithms, and quantum-circuit simulation assistance.
FPGA / ASIC	Real-time control and decoding hardware	Responsible for low-latency feedback, pulse control, fast measurement discrimination, and quantum error-correction syndrome decoding.
QPU	Quantum processing unit	Executes quantum circuits and processes specific subproblems that can benefit from quantum superposition, entanglement, and interference.
Runtime / Orchestrator	Computing coordination layer	Distributes tasks among CPUs, GPUs, FPGAs, and QPUs, deciding which parts should be handled classically and which should be sent to quantum hardware.

Why Do Quantum Computers Need Supercomputers?

A quantum computer is not a universal machine capable of independently processing every task. In practice, most current quantum algorithms require substantial classical computation. For example, in variational quantum algorithms (VQAs), the QPU executes parameterized quantum circuits and outputs measurement results; the classical computer then updates the parameters based on those results and sends the new parameters back to the QPU.

This loop of “QPU execution + classical optimization” makes quantum computing inherently hybrid. As problem sizes grow, the amount of data processing, scheduling, optimization, and error mitigation required on the classical side also increases rapidly. As a result, supercomputing systems will become indispensable infrastructure for large-scale quantum computing.

Hybrid Computing Task	Main Hardware	Function
Quantum Circuit Compilation	CPU / GPU	Converts abstract quantum algorithms into hardware-executable gate sequences while considering qubit topology, coupling maps, and gate errors.
Pulse Generation and Control	AWG / FPGA / Control electronics	Converts quantum gates into microwave pulses, flux pulses, and readout pulses, which are sent into the cryogenic system to control the QPU.
Quantum Circuit Execution	QPU	Executes quantum operations in a cryogenic environment using quantum superposition, entanglement, and interference.
Measurement Result Processing	FPGA / CPU / GPU	Converts weak readout signals into a classical bitstream and performs classification, correction, and statistical analysis.
Error Mitigation and Error Correction	CPU / GPU / FPGA / ASIC	Performs error mitigation in the NISQ era; in fault-tolerant quantum computing, real-time syndrome decoding and feedback control are required.
Workflow Scheduling	HPC / Cloud Runtime	Manages task allocation and data flow among multiple users, multiple QPUs, and different classical computing resources.

Key Concepts in Supercomputer–Quantum Hybrid Architectures

Key Concept	Description
Quantum Runtime	Packages quantum workloads into executable tasks and coordinates QPUs, classical servers, and cloud resources.
Circuit Knitting	Splits a large quantum circuit into multiple smaller circuits, executes them on different QPUs or at different times, and reconstructs the result through classical post-processing.
Error Mitigation	Uses classical statistical methods to reduce the influence of noise on quantum results before fully fault-tolerant hardware is available.
Real-time Feedback	Measurement results must be fed back to the control system within an extremely short time window to support dynamic circuits and quantum error correction.
Resource Orchestration	When a task requires multiple QPUs, multiple GPUs, or multiple classical servers, the system must automatically manage resource allocation and data synchronization.
Quantum Interconnect	As the number of QPUs increases, the system needs links capable of transmitting quantum information between modules.

Typical Workflow of Hybrid Computing

A quantum–classical hybrid computation usually does not end with a single submission of a quantum circuit. Instead, it consists of multiple iterations. The classical side adjusts the parameters of the next quantum circuit according to the results of each measurement round, forming a closed feedback loop.

1. Problem decomposition: Split the original scientific or engineering problem into parts that can be handled classically and parts that may benefit from quantum acceleration.

2. Quantum circuit generation: Generate parameterized quantum circuits or specific quantum kernels on the classical side.

3. Hardware compilation: Perform transpilation based on the QPU topology, native gate set, and calibration data.

4. QPU execution: Execute the circuit on the cryogenic quantum chip and measure the output.

5. Classical post-processing: Use CPUs/GPUs to analyze measurement results, estimate expectation values, and update parameters.

6. Iterative convergence: Repeat the process until the energy, cost function, or target metric converges.

▲ Schematic diagram of hybrid computing in quantum machine learning.
Ref: Quantum-Train: rethinking hybrid quantum-classical machine learning in the model compression perspective, DOI: 10.1007/s42484-025-00305-0

Technical Challenges

Key Challenge	Description
Low-latency Control	Quantum error correction and dynamic circuits require real-time interpretation of measurement results and feedback operations within the coherence time.
Data-flow Bottleneck	Repeated measurements of many qubits generate massive bitstreams, requiring high-speed data acquisition, compression, classification, and storage.
Cross-hardware Scheduling	CPUs, GPUs, FPGAs, QPUs, and cloud servers operate at different rhythms and must be coordinated by a runtime system.
Error-correction Decoding	Fault-tolerant quantum computing requires real-time processing of syndrome information; decoders may require FPGA, ASIC, or GPU acceleration.
Multi-QPU Scaling	The number of qubits in a single QPU is limited. Future systems must expand the effective computational space through modular QPUs and quantum links.
Hardware–Software Co-design	Quantum algorithms, compilers, control pulses, QPU topology, and cryogenic packaging must be designed together rather than optimized separately.

IQM and the Leibniz Supercomputing Centre: An Experiment in Quantum Integration

A 2025 IQM research report (arxiv:2509.12949) summarized practical experience in integrating a 20-qubit superconducting quantum computer into the HPC infrastructure of the Leibniz Supercomputing Centre (LRZ). This case is important because it shows that for a quantum computer to truly become a “quantum accelerator,” the QPU itself is not enough. Site preparation, cooling, networking, scheduling, calibration, and user training must all be integrated.

(Top) Ref: https://thequantuminsider.com/2024/06/19/germany-launches-first-hybrid-quantum-computer-at-leibniz-supercomputing-centre/
(Bottom) Ref: https://arxiv.org/pdf/2509.12949v1

1. Environmental Control

Conventional HPC nodes can usually be treated as stable computing resources: once installed, powered, and connected to cooling systems, they can provide relatively stable computing capacity for long periods. A superconducting quantum computer, however, is closer to a precision experimental apparatus. It is more sensitive to environmental vibration, sound, electromagnetic noise, and temperature fluctuations, because these disturbances can affect qubit coherence times, gate-operation accuracy, and readout quality.

Therefore, before deploying a quantum computer, a data center must conduct a strict site survey, including measurements of magnetic fields, floor vibrations, sound pressure, temperature, and humidity. This means that future quantum data centers will require more than just “power, networking, and cooling.” They must also satisfy requirements for low noise, high stability, and maintainability.

Measurement	Equipment	Requirement
DC magnetic field	A 3-axis fluxgate sensor positioned at the planned location of the cryostat, approximately at the height of the QPU.	< 100 μT for each axis.
AC magnetic field	A 3-axis fluxgate sensor positioned at the planned location of the cryostat, approximately at the height of the QPU.	< 1 μT peak-to-peak spectrum amplitude for each axis over the frequency range 5 Hz – 1000 Hz.
Floor vibrations	A single-axis vibration sensor positioned on the floor at the planned location of the cryostat.	< 400 μm/s RMS spectrum amplitude for each axis over the frequency range 1 Hz – 200 Hz, or equivalently, within the ISO vibration limit for office spaces.
Sound pressure	An omnidirectional microphone positioned at the location of the cryostat.	< 80 dBA when integrated over the frequency range 20 Hz – 20 kHz.
Temperature	A thermometer positioned at the planned location of the electronics cabinet.	ΔT < ±1°C within 12 hours around any set point between 20 – 25°C.
Humidity	A hygrometer positioned at the planned location of the electronics cabinet.	25 – 60%, non-condensing.

2. Calibration and Monitoring: Quantum Computers Are Dynamic Systems

The properties of superconducting qubits change over time. Their frequencies, gate fidelities, readout fidelities, and noise conditions may drift over timescales ranging from hours to days. This is one of the largest differences between quantum computers and conventional CPUs/GPUs: quantum computers require repeated calibration, and such calibration cannot rely entirely on manual operation.

IQM’s 20-qubit superconducting quantum computer includes automated calibration workflows. The system can perform either fast calibration or full calibration, and the HPC center can schedule calibration windows according to user workloads. This is crucial: if a QPU is to become part of an HPC resource pool, calibration must be integrated into the scheduling system in real time, rather than treated as an external maintenance event.

3. The Importance of Backup Power and Cooling Systems

Superconducting quantum computers must operate at extremely low temperatures. If power or cooling is interrupted, the QPU may warm up, requiring the system to be cooled down and recalibrated again. This recovery process may take several days, making it far more complex than restarting an ordinary HPC node.

Therefore, IQM emphasizes the importance of backup power and redundant cooling-water systems. For a data center, the availability of a quantum computer depends not only on the QPU itself, but also on whether the entire infrastructure can prevent unexpected downtime.

4. The Key to HPC+QC: Turning the QPU into a Schedulable Accelerator

In an HPC+QC architecture, a quantum computer can be used in two ways. The first is remote asynchronous submission: users submit quantum tasks to a queue and retrieve results after the QPU executes them. The second is a more tightly integrated accelerator mode: the QPU is embedded into a classical HPC workflow, forming a low-latency hybrid computing loop with CPUs/GPUs. This is especially important for VQE, quantum chemistry, optimization, and hybrid quantum-classical algorithms.

This integration requires a software stack capable of connecting multiple front-end frameworks with hardware backends. The Munich Quantum Software Stack (MQSS), mentioned in the IQM paper, supports interfaces such as Qiskit, CUDA-Q, and PennyLane. Through intermediate representations and JIT compilation, it converts high-level quantum programs into low-level instructions executable by the hardware.

5. User Onboarding: Hardware Availability Does Not Immediately Mean Research Readiness

Even after quantum hardware has been connected to an HPC system, users still need to learn how to use it effectively. For quantum experts, the key is to understand the topology, native gate set, and noise characteristics of a specific QPU. For traditional HPC users, the first step is to understand the basic concepts of quantum circuits, quantum measurement, and hybrid workflows.

Therefore, successful HPC+QC integration is not only a technical issue but also a user-education issue. The IQM case uses Jupyter notebooks, hardware-characterization tutorials, mentorship, and FAQs to help early users move from “having access to a quantum computer” toward “producing meaningful research results.”

The IQM case shows that bringing quantum computers into the HPC world cannot be done simply by placing a QPU inside a data center. True HPC+QC integration requires five layers to mature together:

• A low-noise site and environmental control suitable for quantum hardware;
• Automated calibration workflows that can be managed by HPC scheduling systems;
• Stable power, cooling, and redundant infrastructure;
• A software stack that supports both remote submission and low-latency hybrid computing;
• Training and onboarding mechanisms for both quantum experts and HPC users.

Future quantum computing will not simply be the scaling of a single QPU. It will be the integration of “QPU + HPC + software stack + data-center engineering + user ecosystem.”

IBM Quantum System Two: A Scalable Quantum–Supercomputing Architecture

▲ Conceptual renderings of IBM Quantum System Two. The focus of such systems is not merely the qubit count of a single QPU, but how cryogenic systems, classical control electronics, data-center infrastructure, and multiple quantum processors can be integrated into a scalable computing platform. The vision of a quantum-centric supercomputer is not simply to scale up a single QPU, but to integrate multiple quantum systems, classical servers, and data-center networks. The coexistence of classical connections and quantum connections indicates that future large-scale quantum computing will require both classical data flow and quantum information flow.
Ref: IBM Quantum, 100,000-qubit quantum-centric supercomputer vision.
(Top) Ref: https://newsroom.ibm.com/2023-05-21-IBM-Launches-100-Million-Partnership-with-Global-Universities-to-Develop-Novel-Technologies-Towards-a-100,000-Qubit-Quantum-Centric-Supercomputer
(Bottom) Ref: https://www.ibm.com/quantum/blog/supercomputing-24

▲ Promotional video of IBM Quantum System Two.
Ref: https://www.youtube.com/watch?v=AQjKUN8PORM

NVIDIA NVQLink: A Modular Interface for Quantum–Supercomputing Integration

▲ NVIDIA’s NVQLink clearly plays the role of an intermediary between supercomputers and QPUs. NVQLink is not merely an information exchanger; it also integrates instruments from quantum-control hardware vendors in order to operate the QPU. More specifically, NVQLink acts as a high-speed signal translator: it converts HPC requests into quantum-computer control signals, sends them to the quantum chip for computation, and translates quantum results back to the HPC system. In addition, because quantum chips require complex real-time QEC control, the quantum-control instruments integrated with NVQLink can also participate in error correction and calibration during quantum computation. NVQLink can therefore be understood as a solution that modularizes the interface between classical high-speed computing and quantum computing. Classical HPC systems do not need to take on the computational burden of quantum control, calibration, and optimization, while quantum-chip vendors only need to adapt their systems to the NVQLink interface. In future hybrid-computing workflows, this provides a modular solution: NVQLink + QPU can be introduced into existing HPC frameworks without redesigning the classical architecture specifically for quantum computing.
Ref: https://developer.nvidia.com/blog/nvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/

In summary, the first-layer problem of ultra-large-scale quantum computing is how to make QPUs usable accelerators within high-performance computing systems. This requires the integration of runtimes, compilers, classical accelerators, low-latency control, and error-correction decoding.

Originally written in Chinese by the author, these articles are translated into English to invite cross-language resonance.