Hardware Guide

For superconducting quantum computers, as the number of qubits increases, chip area, wiring density, frequency allocation, microwave crosstalk, fabrication yield, packaging complexity, and the requirements of quantum error correction all become rapidly more demanding. To realize a truly scalable quantum computer, the key question is not only “how to fabricate more qubits,” but how to make a large number of qubits operate together under conditions that allow reliable control, readout, and error correction.

Therefore, the development direction of large-scale QPUs is gradually moving from a “single giant chip” toward a modular quantum system. In other words, a future QPU may not necessarily be one extremely large chip, but rather a quantum computing cluster composed of multiple quantum chips, multiple packaging modules, or even multiple dilution refrigerators. In this context, quantum interconnection becomes a core technology for realizing a scalable QPU.

Scaling Approach	Advantages	Main Bottlenecks
Scaling up a single chip	The architecture is intuitive, the coupling distance within the chip is short, and the control model is relatively simple.	Chip area, wiring density, fabrication yield, frequency crowding, and crosstalk increase rapidly.
Multiple chips inside a single refrigerator	The total number of qubits can be increased through chiplet, packaging, and modular technologies.	The cryogenic space is limited, and packaging, vertical interconnection, and synchronized control become more complex.
Quantum links across multiple refrigerators	QPUs can be distributed across multiple cryostats to form a larger quantum computing cluster.	Low-loss, low-thermal-noise, phase-stable, and synchronizable quantum channels are required.

From a Single Chip to a Modular QPU

IBM Quantum’s development roadmap clearly illustrates this modularization trend. Early quantum processors mainly emphasized increasing the number of qubits on a single chip, such as the Hummingbird, Eagle, Osprey, and Condor processors. However, as systems move toward higher qubit counts and stronger error-correction requirements, simply enlarging a single chip is no longer sufficient for long-term scaling.

Therefore, IBM’s architecture has begun to move toward multi-chip, multi-module, and multi-system parallelization. For example, the Heron architecture emphasizes higher-quality medium-scale chips; Crossbill and Flamingo represent chip-to-chip connection and modular packaging; Kookaburra further demonstrates the concept of multi-chip quantum parallelization. These developments all point to one central question: How can quantum information be exchanged effectively between different quantum chips?

Here, two different types of connection must be distinguished. The first is a classical link, which uses real-time classical communication to allow multiple QPUs to execute tasks collaboratively. The second is a quantum link, which is a channel that truly transmits quantum states or establishes quantum correlations. The former is easier to implement, while the latter is closer to the core capability required for future large-scale fault-tolerant quantum computers.





▲ IBM quantum processors are moving from single-chip scaling toward multi-chip modularization. Condor represents the scaling of the qubit count on a single chip, while Flamingo, Crossbill, and Kookaburra begin to introduce chip-to-chip quantum communication and modular scaling. It is worth noting that interconnections inside chips can be divided into classical interconnections and quantum interconnections. Classical interconnections are basically used for microwave control/readout signals, whereas quantum interconnections require the interactions between chips to preserve quantum effects.
Ref: https://spectrum.ieee.org/ibm-condor





▲ IBM Quantum Crossbill (left) and IBM Quantum Condor (right). Condor adopts a monolithic large-chip design, while Crossbill uses a multi-chip interconnection design.
Ref: https://www.ibm.com/quantum/blog/qdc-2024





▲ Two IBM Quantum Eagle processors are connected through a real-time classical link. This architecture allows multiple QPUs to work collaboratively within the same system, but it still belongs to classical communication and is different from a true quantum interconnect.
Ref: https://www.ibm.com/quantum/blog/lo-locc-circuit-cutting





▲ The interconnection architecture of IBM Heron mainly uses a shared microwave signal bus for control/readout. Since the current microwave signals for control/readout are classical control signals, this type of interconnection is classified as a classical interconnection.
Ref: https://www.ibm.com/quantum/blog/ibm-quantum-roadmap-2025



Three Levels of Quantum Interconnection: C-coupler, M-coupler, and L-coupler

IBM classifies quantum interconnections according to different length scales. Some interconnections are used inside the same chip to increase the connectivity between non-neighboring qubits; some are used between adjacent chips to form multi-chip modules; others are responsible for connecting more distant chip platforms inside the same dilution refrigerator. These interconnection technologies target quantum networks within the same refrigerator.

Interconnection Type	Connection Scale	Functional Description
C-coupler	Between non-neighboring qubits within the same chip	The C-coupler is used to improve intra-chip connectivity, allowing distant and non-neighboring qubits on the same chip to transmit quantum information. This is particularly important for certain quantum error-correction codes, because error correction does not necessarily rely only on nearest-neighbor qubit interactions.
M-coupler	Interconnection between adjacent chips	The M-coupler is a short-distance chip-to-chip quantum interconnect used to transmit quantum information between adjacent quantum chips. It is suitable for combining several smaller chips into a larger modular quantum processor.
L-coupler	Between more distant chips inside the same refrigerator	The L-coupler is a longer-distance quantum interconnection that can route quantum information between different platforms or more distant chips inside the same cryostat. As the transmission distance increases, it places higher demands on loss, latency, phase stability, and synchronized control.




▲ (Left) C-coupler: Used to improve qubit connectivity within the same chip. In many quantum error-correction architectures, qubits not only need to interact with nearest neighbors, but may also need to transmit information to more distant qubits. The goal of the C-coupler is to establish effective quantum communication paths between non-neighboring qubits.
(Middle) M-coupler: Used for short-distance interconnection between adjacent quantum chips. It can transmit quantum information between neighboring chips and is suitable for combining several smaller chips into a larger modular quantum processor.
(Right) L-coupler: Used for longer-distance quantum interconnection. It can transmit quantum information between quantum chips on different platforms inside the same refrigerator, meaning that quantum chips do not all have to be packed into the same local packaging region. However, the increased distance also brings stricter limits on loss, latency, and transmission rate.
Ref: IEEE Spectrum / IBM, Optics Lab





▲ The M-coupler allows multiple quantum processors to work together through connection channels, so quantum computing is no longer limited to a single chip.
Ref: https://www.ibm.com/quantum/blog/ibm-quantum-roadmap-2025





▲ The L-coupler used for IBM Flamingo demonstrates the design direction of modular quantum processors and long-distance connection. The focus of this type of architecture is not only to increase the number of qubits, but also to allow multiple quantum modules to operate together under synchronized and controllable conditions.
Ref: https://www.ibm.com/quantum/blog/qdc-2024
Ref: https://www.forbes.com/sites/karlfreund/2023/12/04/ibm-launches-quantum-system-two-and-a-roadmap-to-quantum-advantage/








▲ C-, M-, and L-couplers can be used together to expand quantum chip interconnection.
Ref: Forbes (https://www.forbes.com/sites/karlfreund/2023/12/04/ibm-launches-quantum-system-two-and-a-roadmap-to-quantum-advantage/) / IBM





▲ Kookaburra demonstrates the concept of parallelized interconnection among multi-chip quantum processors. Multiple quantum chips are connected through quantum links to form a larger processing unit.
Ref: https://www.ibm.com/quantum/blog/ibm-quantum-roadmap-2025






From these three types of interconnection, we can see that the scaling of large quantum computers actually involves multiple levels: the first level is qubit connectivity within the same chip; the second level is chip-to-chip interconnection between adjacent chips; the third level is long-distance connection between different shielding cans inside the same refrigerator; beyond that comes the inter-cryostat quantum link between multiple refrigerators.

Why Does Error Correction Require Higher Connectivity?

In small quantum processors, nearest-neighbor coupling is usually sufficient for executing many basic quantum circuits. However, in QEC architectures, the situation becomes more complex. Many efficient quantum error-correction codes, such as LDPC codes, may require higher non-local connectivity between qubits. If all interactions must be completed through nearest-neighbor swaps, additional SWAP gates will be introduced, increasing circuit depth and accumulating more errors.




qLDPC Quantum Error Correction

In 2024, IBM demonstrated work on qLDPC quantum error correction. QEC codes play a very important role in practical computation, and how to achieve optimal information transmission and error-correction redundancy with minimal overhead has always been an engineering trade-off. Because quantum computation has the feature that quantum information cannot be directly measured without disturbance, quantum error correction becomes even more difficult. Superconducting qubits are implemented on two-dimensional quantum chips, and the current mainstream quantum error-correction approach is the surface code. The advantage of the surface code is that its connectivity requirement only involves neighboring qubits and does not require long-range interactions. Its disadvantage is that the number of ancilla qubits increases together with the system size, which in practice increases system complexity and error sources. In 2024, IBM demonstrated quantum error-correction operations based on qLDPC (quantum Low-Density Parity Check code) combined with the surface code. qLDPC requires long-range interactions, and IBM’s multilayer chip fabrication wiring/C-coupler enables more complex inter-qubit connectivity topologies.





▲ A comparison in IBM’s paper between the conventional surface code and a new, efficient bivariate bicycle code, abbreviated as BB code, which is a type of qLDPC code.
Figure a. The surface code.
Figure b. The geometry of the BB code, or bivariate bicycle code: it is “embedded” on a topological torus, shaped like a donut, where each qubit has six lines connected to it, including four short-range and two long-range connections.
Figure c. The hybrid architecture and operations.
To reach the same fault-tolerance level, a conventional surface code may require thousands of qubits, while the BB code only requires a little more than one hundred.
Ref: 10.1038/s41586-024-07107-7





▲ A schematic drawn by IBM showing the BB code embedded on the topological torus mentioned above.
Ref: https://www.ibm.com/quantum/blog/large-scale-ftqc


Therefore, the significance of the C-coupler, M-coupler, and L-coupler is not merely to “connect chips together,” but to provide a more flexible connectivity graph for future error-corrected logical qubits. From this perspective, quantum interconnection is not only a hardware packaging problem; it also directly affects quantum error-correction codes, compilation strategies, and system architecture.




From Expanding Quantum Chips to Quantum Data Centers: Toward Ultra-Large-Scale Quantum Computing

When quantum computers move from a single QPU toward quantum data centers, the system architecture becomes closer to a hybrid quantum-classical infrastructure. In this architecture, the QPU is responsible for quantum-state evolution and quantum measurement; the classical cluster is responsible for compilation, scheduling, optimization, error decoding, and feedback; and the runtime system is responsible for assigning quantum tasks to suitable hardware resources.



▲ IBM’s conceptual image of hybrid supercomputing-quantum computing. Scaled qubit computation will move from on-chip interconnection, cross-chip interconnection, and intra-refrigerator cross-package interconnection toward inter-refrigerator quantum interconnection, which will be introduced further in a later article.
(Top)Ref: https://spectrum.ieee.org/ibm-quantum-computer-2668978269
(Bottom)Ref: https://www.forbes.com/sites/karlfreund/2023/12/04/ibm-launches-quantum-system-two-and-a-roadmap-to-quantum-advantage/



Therefore, the core of a scalable QPU is not a breakthrough at a single level, but the joint maturation of multiple levels: better qubit connectivity is needed inside the chip; low-loss chip-to-chip quantum interconnects are needed between chips; long-distance and phase-stable quantum channels are needed inside the refrigerator; and inter-cryostat links capable of maintaining synchronization and quantum correlations are needed between multiple refrigerators.

From the development of IBM Quantum, we can see that the C-coupler, M-coupler, and L-coupler represent quantum interconnections at different length scales: from the connection of non-neighboring qubits within a chip, to short-distance connection between adjacent chips, and then to longer-distance quantum connection inside the same refrigerator. Together, they point to an important direction: the future of quantum computers is not only about larger chips, but about better quantum-networked architectures.

Originally written in Chinese by the author, these articles are translated into English to invite cross-language resonance.